DISPS-P3: High Performance DSP Architectures and Systems |
| Session Type: Poster |
| Time: Friday, May 21, 13:00 - 15:00 |
| Location: Poster Area 3 |
| Chair: Liang-Gee Chen, National Taiwan University |
| DISPS-P3.1: A DATA MERGING TECHNIQUE FOR HIGH-SPEED LOW-POWER MULTIPLY ACCUMULATE UNITS |
| Ayman Fayed; Intel Corporation |
| Walid Elgharbawy; University of Louisiana at Lafayette |
| Magdy Bayoumi; University of Louisiana at Lafayette |
| DISPS-P3.2: A SOFTWARE / HARDWARE CODESIGNED HANDS FREE SYSTEM ON A "RESIZABLE" BLOCK-FLOATING-POINT DSP |
| Shiro Kobayashi; Asahi Kasei Corporation |
| Isamu Kozuka; Asahi Kasei Corporation |
| Wai Hung Tang; Asahi Kasei Corporation |
| Diemo Landmann; Asahi Kasei Corporation |
| DISPS-P3.3: PARALLEL GLOBAL ELIMINATION ALGORITHM AND ARCHITECTURE DESIGN FOR FAST BLOCK MATCHING MOTION ESTIMATION |
| Yu-Wen Huang; National Taiwan University |
| Chen-Han Tsai; National Taiwan University |
| Liang-Gee Chen; National Taiwan University |
| DISPS-P3.4: AN EFFICIENT RESIDUE TO ANALOG CONVERTER |
| Michael Lewis; The Athena Group, Inc. |
| Jon Mellott; The Athena Group, Inc. |
| Fred Taylor; University of Florida |
| DISPS-P3.5: A NOVEL HIGH PERFORMANCE DISTRIBUTED ARITHMETIC ADAPTIVE FILTER IMPLEMENTATION ON AN FPGA |
| Daniel Allred; Georgia Institute of Technology |
| Heejong Yoo; Georgia Institute of Technology |
| Venkatesh Krishnan; Georgia Institute of Technology |
| Walter Huang; Georgia Institute of Technology |
| David Anderson; Georgia Institute of Technology |
| DISPS-P3.6: IMPLEMENTATION OF RECURSIVE DIGITAL FILTERS INTO VECTOR SIMD DSP ARCHITECTURES |
| Pablo Robelly; Technische Universität Dresden |
| Gordon Cichon; Technische Universität Dresden |
| Hendrik Seidel; Technische Universität Dresden |
| Gerhard Fettweis; Technische Universität Dresden |
| DISPS-P3.7: ON THE SIMULATION AND DEVELOPMENT OF MASSIVE PARALLEL DIGITAL ARCHITECTURES FOR MARKOV RANDOM FIELDS |
| Stephan Christoph Stilkerich; EADS Corporate Research Center |
| Rupert Reiger; EADS Corporate Research Center |
| DISPS-P3.8: AN LDPC DECODING SCHEDULE FOR MEMORY ACCESS REDUCTION |
| Kiran Gunnam; Texas A&M University |
| Gwan Choi; Texas A&M University |
| Mark Yeary; University of Oklahoma |
| DISPS-P3.9: EFFICIENT VLSI IMPLEMENTATION OF INVERSE DISCRETE COSINE TRANSFORM |
| Jooheung Lee; Pennsylvania State University |
| Vijaykrishnan Narayanan; Pennsylvania State University |
| Mary Jane Irwin; Pennsylvania State University |
| DISPS-P3.10: PARAMETERIZED AND ENERGY EFFICIENT ADAPTIVE BEAMFORMING ON FPGAS USING MATLAB/SIMULINK |
| Jingzhao Ou; University of Southern California |
| Viktor Prasanna; University of Southern California |
| DISPS-P3.11: HARDWARE EFFICIENT LOSSLESS IMAGE COMPRESSION ENGINE |
| Lane Brooks; SMaL Camera Technologies |
| Keith Fife; SMaL Camera Technologies |
| DISPS-P3.12: A REALTIME, MEMORY EFFICIENT FINGERPRINT VERIFICATION SYSTEM |
| Shenglin Yang; University of California, Los Angeles |
| Ingrid Verbauwhede; University of California, Los Angeles |
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